The present invention relates to a semiconductor device having a protective element between an input terminal and an internal circuit.
Recently, an insulate gate field effect transistor (hereinafter abbreviated to IGFET) in an internal circuit of a semiconductor device employs a very thin silicon oxide film such as of 200 to 300 .ANG. thickness as its gate insulating film, and therefore, an effective protective circuit must be provided between the input terminal and the internal circuit for protecting the gate insulating film from external abnormal surge voltages such as noise voltages of high level and/or a large amount of electrostatic charges applied to the input terminal. The protective circuit and protective elements constituting the protective circuit was disclosed, for example, by Jack K. Keller, entitled "PROTECTION OF MOS INTEGRATED CIRCUITS FROM DESTRUCTION BY ELECTROSTATIC DISCHARGE" in "ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS" SESSION 3, pp. 73 to 80, Reliability Analysis Center 1980.
FIG. 1 shows a protective circuit in which first and second resistors R.sub.1 and R.sub.2 are connected in series each other and provided between an input terminal P and a gate electrode of an IGFET Q.sub.3 to be protected in an internal circuit. An IGFET Q.sub.1 serving as a protective element is connected at its gate electrode to a first node N.sub.1 between the input terminal P constituted by a bonding pad and the first resistor R.sub.1, at its drain region to a second node N.sub.2 between the first and second resistors R.sub.1, R.sub.2 and at its source region to a ground potential line, and an IGFET Q.sub.2 serving as a protective element is connected at its gate electrode and source region to the ground potential line in common and at its drain region to a third node N.sub.3 between the second resistor R.sub.2 and the gate electrode of the IGFET Q.sub.3 to be protected. The first and second resistor elements R.sub.1, R.sub.2 are formed in a semiconductor substrate as impurity diffusion regions of a conductivity type opposite to that of the substrate. For example, when the substrate is of P-type, the impurity diffusion regions as the resistor elements are of N-type. Therefore, the PN junction capacitance component is provided in addition to the resistance component, and a peak of the surge voltage can be decreased by the resistance and capacitance components in the resistor element. Further, the resistor elements R.sub.1, R.sub.2 have a function to limit a current flowing the IGFET's Q.sub.1, Q.sub.2 when they are in a conductive state. IGFET Q.sub.2 has the same thin gate insulating film as that of the IGFET Q.sub.3 to be protected, and when the excess surge voltage appears at the node N.sub.3 and be applied between the source and drain regions, the IGFET Q.sub.2 conducts a punch-through phenomenon between source and drain regions thereof so that the surge voltage at the node N.sub.3 is depressed to the earth potential and the gate insulating film of the IGFET Q.sub.3 is protected. On the other hand, as the gate electrode of the IGFET Q.sub.1 is connected to the node N.sub.1, that is, to the input terminal, the severest state of the surge voltage influences directly on the gate insulating film of the IGFET Q.sub.1. Therefore, the IGFET Q.sub.1 employs a thick field insulating layer or the thick field insulating layer and an inter-ply insulating layer thereon as the gate insulating film so that the IGFET Q.sub.1 per se is not destroyed by the surge voltage. The threshold voltage of the IGFET Q.sub.1 becomes a high level such as 20 to 30 volts because of the thick gate insulating film, and when a high surge voltage of 20 to 30 volts or more is applied to the input terminal P, the IGFET Q.sub.1 turns to a conductive state to depress the surge voltage at the node N.sub.2 to the earth potential. The present invention concerns the structure of the IGFET Q.sub.1.
When a high surge voltage of 20 to 30 volts or more is applied to the input terminal, an N-type inversion layer is induced under the thick gate insulating film, that is, at the channel region of the IGFET Q.sub.1, and electrons flow from the N-type source region to the N-type drain region through the inversion layer. In this case, many electrons run by repeating collisions with silicon atoms in the inversion layer. Therefore, their energy becomes a low level, and the low energy electrons are drawn to the drain region. However, some lucky electrons run without the collisions or with a small number of times of collisions, and keep a high energy. The lucky electrons (hot electrons) have a high energy sufficient to get over the barrier of a silicon oxide, and therefore, they are introduced into a part near the drain region of a side wall of the field insulating layer made of silicon oxide as the gate insulating film, and trapped therein.
In a prior art, the drain region of the IGFET Q.sub.1 is attached to an upper part of the side wall of the embedded field insulating layer as the gate insulating film, and the lucky electrons (hot electrons) are trapped in a lower part under the upper part of the side wall. The trapped electrons induce positive charges in the substrate in the vicinity of the trapping part (lower part) of the side wall, and therefore, in the prior art, the induced positive charges are positioned near the drain region and the breakdown voltage of the drain region becomes a low level by the induced positive charges. Consequently, when an normal voltage, that is, an operating voltage is applied to the input line through the input terminal to operate the internal circuit (the internal circuit is an inherent circuit of the semiconductor device, and operates and conducts the functions of the device by the operating voltage), an unfavorable leakage current is flown from the drain region of the protective IGFET Q.sub.1 to the substrate because of the low breakdown voltage nature. Therefore, a high reliable semiconductor device cannot be obtained.